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| Features * Programmable Audio Output for Interfacing with Common Audio DAC * * * * * * * * * * * * * * * * * - PCM Format Compatible - I2S Format Compatible 8-bit MCU C51 Core-based (FMAX = 20 MHz) 2304 Bytes of Internal RAM 64K Bytes of Code Memory - AT89C5132: Flash (100K Write/Erase Cycles) 4K Bytes of Boot Flash Memory (AT89C5132) - ISP: Download from USB or UART to any External Memory Cards USB Rev 1.1 Device Controller - "Full Speed" Data Transmission Built-in PLL MultiMedia Card(R) Interface Compatibility Atmel DataFlash(R) SPI Interface Compatibility IDE/ATAPI Interface 2 Channels 10-bit ADC, 8 kHz (8 True Bits) - Battery Voltage Monitoring - Voice Recording Controlled by Software Up to 44 Bits of General-purpose I/Os - 4-bit Interrupt Keyboard Port for a 4 x n Matrix - SmartMedia(R) Software Interface Two Standard 16-bit Timers/Counters Hardware Watchdog Timer Standard Full Duplex UART with Baud Rate Generator Two Wire Master and Slave Modes Controller SPI Master and Slave Modes Controller Power Management - Power-on Reset - Software Programmable MCU Clock - Idle Mode, Power-down Mode Operating Conditions - 3V, 10%, 25 mA Typical Operating at 25C - Temperature Range: -40C to +85C Packages - TQFP80, PLCC84 (Development Board Only) - Dice USB Microcontroller with 64K Bytes Flash Memory AT89C5132 Preliminary Summary * * Description The AT89C5132 is a mass storage device controlling data exchange between various Flash modules, HDD and CD-ROM. The AT89C5132 includes 64K Bytes of Flash memory and allows In-System Programming through an embedded 4K Bytes of Boot Flash Memory. The AT89C5132 include 2304 Bytes of RAM memory. The AT89C5132 provides all the necessary features for man-machine interface including, timers, keyboard port, serial or parallel interface (USB, SPI, IDE), ADC input, I2S output, and all external memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards). Typical Applications * * * Flash Recorder/Writer PDA, Camera, Mobile Phone PC Add-on Rev. 4173CS-USB-07/04 Block Diagram Figure 1. AT89C5132 Block Diagram INT0 INT1 VDD VSS UVDD UVSS AVDD AVSS AREF AIN1:0 TXD RXD T0 T1 SS MISO MOSI SCK SCL SDA 1 1 Interrupt Handler Unit Flash RAM 2304 Bytes 64K Bytes Flash Boot 4K Bytes 10-bit A-to-D Converter 1 1 1 1 2 2 2 2 1 1 UART and BRG Timers 0/1 Watchdog SPI/DataFlash Controller TWI Controller C51 (X2 CORE) 8-BIT INTERNAL BUS Clock and PLL Unit I2S/PCM Audio Interface USB Controller MMC Interface Keyboard Interface I/O Ports IDE Interface 3 FILT X1 X2 RST DOUT DCLK DSEL SCLK D+ DMCLK MDAT MCMD KIN3:0 P0 - P5 Notes: 1. Alternate function of Port 3 2. Alternate function of Port 4 3. Alternate function of Port 1 4 AT89C5132 4173CS-USB-07/04 AT89C5132 Pin Description Figure 2. AT89C5132 80-pin TQFP Package P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 ALE ISP P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6/SCL P1.7/SDA VDD PVDD FILT PVSS VSS X2 X1 TST UVDD UVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 TQFP80 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS VDD MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS VDD D+ DVDD VSS P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 5 4173CS-USB-07/04 Figure 3. AT89C5132 84-pin PLCC (1) NC P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 ALE ISP P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6/SCL P1.7/SDA VDD PAVDD FILT PAVSS VSS X2 NC X1 TST UVDD UVSS 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 PLCC84 NC P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS VDD MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS VDD Note: 1. For development board only. 6 AT89C5132 4173CS-USB-07/04 D+ DVDD VSS P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3 NC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 AT89C5132 Signals All the AT89C5132 signals are detailed by functionality in Table 1 to Table 15. Table 1. Ports Signal Description Signal Name Type Description Port 0 P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, floating P0 inputs must be polarized to VDD or VSS. Port 1 P1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 P2 is an 8-bit bidirectional I/O port with internal pull-ups. Alternate Function P0.7:0 I/O AD7:0 P1.7:0 I/O KIN3:0 SCL SDA A15:8 RXD TXD P2.7:0 I/O P3.7:0 I/O Port 3 P3 is an 8-bit bidirectional I/O port with internal pull-ups. INT0 INT1 T0 T1 WR RD MISO MOSI SCK SS - P4.7:0 I/O Port 4 P4 is an 8-bit bidirectional I/O port with internal pull-ups. P5.3:0 I/O Port 5 P5 is a 4-bit bidirectional I/O port with internal pull-ups. Table 2. Clock Signal Description Signal Name Type Description Input to the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. X1 is the clock source for internal timing. Output of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave X2 unconnected. PLL Low Pass Filter input FILT receives the RC network of the PLL low pass filter. Alternate Function X1 I - X2 O - FILT I - 7 4173CS-USB-07/04 Table 3. Timer 0 and Timer 1 Signal Description Signal Name Type Description Timer 0 Gate Input INT0 serves as external run control for timer 0, when selected by GATE0 bit in TCON register. INT0 I External Interrupt 0 INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0 is set by a falling edge on INT0#. If bit IT0 is cleared, bit IE0 is set by a low level on INT0#. Timer 1 Gate Input INT1 serves as external run control for timer 1, when selected by GATE1 bit in TCON register. INT1 I External Interrupt 1 INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set, bit IE1 is set by a falling edge on INT1#. If bit IT1 is cleared, bit IE1 is set by a low level on INT1#. Timer 0 External Clock Input When timer 0 operates as a counter, a falling edge on the T0 pin increments the count. Timer 1 External Clock Input When timer 1 operates as a counter, a falling edge on the T1 pin increments the count. P3.3 P3.2 Alternate Function T0 I P3.4 T1 I P3.5 Table 4. Audio Interface Signal Description Signal Name DCLK DOUT DSEL Type O O O Description DAC Data Bit Clock DAC Audio Data DAC Channel Select Signal DSEL is the sample rate clock output. DAC System Clock SCLK is the oversampling clock synchronized to the digital audio data (DOUT) and the channel selection signal (DSEL). Alternate Function - SCLK O - Table 5. USB Controller Signal Description Signal Name Type Description USB Positive Data Upstream Port This pin requires an external 1.5 K pull-up to VDD for full speed operation. USB Negative Data Upstream Port Alternate Function D+ I/O - D- I/O - Table 6. 8 AT89C5132 4173CS-USB-07/04 AT89C5132 Table 7. MutiMediaCard Interface Signal Description Signal Name MCLK Type O Description MMC Clock output Data or command clock transfer. MMC Command line Bidirectional command channel used for card initialization and data transfer commands. To avoid any parasitic current consumption, unused MCMD input must be polarized to VDD or VSS. MMC Data line Bidirectional data channel. To avoid any parasitic current consumption, unused MDAT input must be polarized to VDD or VSS. Alternate Function - MCMD I/O - MDAT I/O - Table 8. UART Signal Description Signal Name Type Description Receive Serial Data RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2 and 3. Transmit Serial Data TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3. Alternate Function RXD I/O P3.0 TXD O P3.1 Table 9. SPI Controller Signal Description Signal Name Type Description SPI Master Input Slave Output Data Line When in master mode, MISO receives data from the slave peripheral. When in slave mode, MISO outputs data to the master controller. SPI Master Output Slave Input Data Line When in master mode, MOSI outputs data to the slave peripheral. When in slave mode, MOSI receives data from the master controller. SPI Clock Line When in master mode, SCK outputs clock to the slave peripheral. When in slave mode, SCK receives clock from the master controller. SPI Slave Select Line When in controlled slave mode, SS enables the slave mode. Alternate Function MISO I/O P4.0 MOSI I/O P4.1 SCK I/O P4.2 SS I P4.3 Table 10. TWI Controller Signal Description Signal Name Type Description TWI Serial Clock When TWI controller is in master mode, SCL outputs the serial clock to the slave peripherals. When TWI controller is in slave mode, SCL receives clock from the master controller. TWI Serial Data SDA is the bidirectional Two Wire data line. Alternate Function SCL I/O P1.6 SDA I/O P1.7 9 4173CS-USB-07/04 Table 11. A/D Converter Signal Description Signal Name AIN1:0 AREFP AREFN Type I I I Description A/D Converter Analog Inputs Analog Positive Voltage Reference Input Analog Negative Voltage Reference Input This pin is internally connected to AVSS. Alternate Function - Table 12. Keypad Interface Signal Description Signal Name Type Description Keypad Input Lines Holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt. Alternate Function KIN3:0 I P1.3:0 Table 13. External Access Signal Description Signal Name Type Description Address Lines Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. Address/Data Lines Multiplexed lower address and data lines for the external memory or the IDE interface. Address Latch Enable Output ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A7:0. An external latch is used to demultiplex the address from address/data bus. ISP Enable Input This signal must be held to GND through a pull-down resistor at the falling reset to force execution of the internal bootloader. Read Signal Read signal asserted during external data memory read operation. Write Signal Write signal asserted during external data memory write operation. Alternate Function A15:8 I/O P2.7:0 AD7:0 I/O P0.7:0 ALE O - ISP I/O - RD O P3.7 WR O P3.6 10 AT89C5132 4173CS-USB-07/04 AT89C5132 Table 14. System Signal Description Signal Name Type Description Reset Input Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage lower than VIL is applied, whether or not the oscillator is running. This pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and VDD. Asserting RST when the chip is in Idle mode or Power-Down mode returns the chip to normal operation. Test Input Test mode entry signal. This pin must be set to VDD. Alternate Function RST I - TST I - Table 15. Power Signal Description Signal Name VDD Type PWR Description Digital Supply Voltage Connect these pins to +3V supply voltage. Circuit Ground Connect these pins to ground. Analog Supply Voltage Connect this pin to +3V supply voltage. Analog Ground Connect this pin to ground. PLL Supply voltage Connect this pin to +3V supply voltage. PLL Circuit Ground Connect this pin to ground. USB Supply Voltage Connect this pin to +3V supply voltage. USB Ground Connect this pin to ground. Alternate Function - VSS GND - AVDD PWR - AVSS GND - PVDD PWR - PVSS GND - UVDD PWR - UVSS GND - 11 4173CS-USB-07/04 Internal Pin Structure Table 16. Detailed Internal Pin Structure Circuit(1) VDD Type Pins RTST Input TST VDD Watchdog Output P Input/Output RRST RST VSS 2 osc periods Latch Output VDD VDD VDD P1 P2 P3 Input/Output N VSS VDD P1(2) P2(3) P3 P4 P53:0 P Input/Output N VSS VDD P0 MCMD MDAT ISP PSEN P Output N VSS ALE SCLK DCLK DOUT DSEL MCLK D+ D- Input/Output D+ D- Notes: 1. For information on resistors value, input/output levels, and drive capability, refer to the Section "DC Characteristics", page 183. 2. When the Two Wire controller is enabled, P1, P2, and P3 transistors are disabled allowing pseudo open-drain structure. 3. In Port 2, P1 transistor is continuously driven when outputting a high level bit address (A15:8). 12 AT89C5132 4173CS-USB-07/04 AT89C5132 Address Spaces The AT8xC5132 derivatives implement four different address spaces: * * * * Code Memory Program/Code Memory Boot Memory Data Memory Special Function Registers (SFRs) The AT89C5132 implements 64K Bytes of on-chip program/code memory in Flash technology. The Flash memory increases ROM functionality by enabling in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD voltage. Thus, the AT89C5132 can be programmed using only one voltage and allows in application software programming commonly known as IAP. Hardware programming mode is also available using specific programming tools. Boot Memory The AT89C5132 implements 4K Bytes of on-chip boot memory provided in Flash technology. This boot memory is delivered programmed with a standard bootloader software allowing in system programming commonly known as ISP. It also contains some Application Programming Interfaces routines commonly known as API allowing user to develop his own bootloader. The AT89C5132 derivatives implement 2304 bytes of on-chip data RAM. This memory is divided in two separate areas: * * 256 bytes of on-chip RAM memory (standard C51 memory). 2048 bytes of on-chip expanded RAM memory (ERAM accessible via MOVX instructions). Data Memory 13 4173CS-USB-07/04 Peripherals The AT8xC5132 peripherals are briefly described in the following sections. For further details on how to interface (hardware and software) to these peripherals, please refer to the AT8xC5132 complete datasheet. Clock Generator System The AT8xC5132 internal clocks are extracted from an on-chip PLL fed by an on-chip oscillator. Four clocks are generated respectively for the C51 core, the audio interface, and the other peripherals. The C51 and peripheral clocks are derived from the oscillator clock. The audio interface sample rates are also obtained by dividing the PLL output clock. The AT8xC5132 implement five 8-bit ports (P0 to P4) and one 4-bit port (P5). In addition to performing general-purpose I/Os, some ports are capable of external data memory operations; others allow for alternate functions. All I/O Ports are bidirectional. Each Port contains a latch, an output driver and an input buffer. Port 0 and Port 2 output drivers and input buffers facilitate external memory operations. Some Port 1, Port 3 and Port 4 pins serve for both general-purpose I/Os and alternate functions. The AT8xC5132 implement the two general-purpose, 16-bit Timers/Counters of a standard C51. They are identified as Timer 0, Timer 1, and can independently be configured each to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, a Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, a Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The AT8xC5132 implement a hardware Watchdog Timer that automatically resets the chip if it is allowed to time out. The WDT provides a means of recovering from routines that do not complete successfully due to software or hardware malfunctions. The AT8xC5132 implements an audio output interface allowing the decoded audio bitstream to be output in various formats. They are compatible with right and left justification PCM and I2S formats and the on-chip PLL allows connection of almost all commercial audio DAC families available on the market. The AT8xC5132 implements a full-speed Universal Serial Bus Interface. The USB interface can be used for the following purposes: * * Download of files by supporting the USB mass storage class. In-System Programming by supporting the USB firmware upgrade class. Ports Timers/Counters Watchdog Timer Audio Output Interface Universal Serial Bus Interface MultiMedia Card Interface The AT8xC5132 implements a MultiMedia Card (MMC) interface compliant to the V2.2 specification in MultiMedia Card mode. The MMC allows storage of files in removable Flash memory cards that can be easily plugged or removed from the application. It can also be used for In-System Programming. The AT8xC5132 provide an IDE/ATAPI interface allowing connection of devices such as CD-ROM reader, CompactFlashTM cards, Hard Disk Drive, etc. It consists of a 16-bit bidirectional bus part of the low-level ANSI ATA/ATAPI specification. It is provided for mass storage interface but could be used for In-System Programming using CD-ROM. IDE/ATAPI Interface 16 AT89C5132 4173CS-USB-07/04 AT89C5132 Serial I/O Interface The AT89C5132 implements a serial port with its own baud rate generator providing one single synchronous communication mode and three full-duplex Universal Asynchronous Receiver Transmitter (UART) communication modes. It is provided for the following purposes: * * In System Programming. Remote control of the AT89C5132 by a host. Serial Peripheral Interface The AT89C5132 implements a Serial Peripheral Interface (SPI) supporting master and slave modes. It is provided for the following purposes: * * Remote control of the AT89C5132 by a host. In System Programming. Two-wire Controller The AT89C5132 implements a 2-wire controller supporting the four standard master and slave modes with multimaster capability. It is provided for the following purposes: * * * Connection of slave devices like LCD controller, audio DAC... Remote control of the AT89C5132 by a host. In System Programming. A/D Controller The AT89C5132 implements a 2-channel 10-bit (8 true bits) analog to digital converter (ADC). It is provided for the following purposes: * * * Battery monitoring. Voice recording. Corded remote control. 17 4173CS-USB-07/04 Electrical Characteristics Absolute Maximum Ratings Storage Temperature ..................................... -65C to +150C Voltage on any other Pin to VSS ..................................... -0.3 to +4.0V NOTE: IOL per I/O Pin ................................................................. 5 mA Power Dissipation ............................................................. 1 W Ambient Temperature Under Bias.................... -40C to +85C Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "operating conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. VDD ....................................................................................... 2.7V to 3.3V DC Characteristics Digital Logic Table 1. Digital DC Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85C Symbol VIL VIH1 VIH2 VOL1 Parameter Input Low Voltage Input High Voltage (except RST, X1) Input High Voltage (RST, X1) Output Low Voltage (except P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) Output Low Voltage (P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) Output High Voltage (P1, P2, P3, P4 and P5) Output High Voltage (P0, P2 address mode, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT, D+, D-) Logical 0 Input Current (P1, P2, P3, P4 and P5) VDD - 0.7 Min -0.5 0.2*VDD + 1.1 0.7*VDD(2) Typ(1) Max 0.2*VDD - 0.1 VDD VDD + 0.5 0.45 Units V V V Test Conditions V IOL= 1.6 mA VOL2 0.45 V IOL= 3.2 mA VOH1 V IOH= -30 A VOH2 VDD - 0.7 V IOH= -3.2 mA IIL -50 A Vin = 0.45 V 18 AT89C5132 4173CS-USB-07/04 AT89C5132 Table 1. Digital DC Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85C Symbol Parameter Input Leakage Current (P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) Logical 1 to 0 Transition Current (P1, P2, P3, P4 and P5) Pull-Down Resistor Pin Capacitance VDD Data Retention Limit 50 90 10 1.8 X1 / X2 mode 6.5 / 10.5 8 / 13.5 9.5 / 17 X1 / X2 mode 5.3 / 8.1 6.4 / 10.3 7.5 / 13 500 Min Typ(1) Max Units A Test Conditions ILI 10 0.45< VIN< VDD ITL RRST CIO VRET -650 200 A k pF V Vin = 2.0 V TA= 25C VDD < 3.3 V mA 12 MHz 16 MHz 20 MHz VDD < 3.3 V mA 12 MHz 16 MHz 20 MHz VRET < VDD < 3.3 V IDD Operating Current (3) IDL Idle Mode Current (3) IPD Power-Down Mode Current 20 A Notes: 1. Typical values are obtained using VDD= 3 V and TA= 25C. They are not tested and there is no guarantee on these values. 2. Flash retention is guaranteed with the same formula for VDD min down to 0V. 3. See Table 154 for typical consumption in player mode. IDD, IDL and IPD Test Conditions Figure 1. IDD Test Condition, Active Mode VDD VDD RST VDD PVDD UVDD AVDD IDD (NC) Clock Signal X2 X1 P0 VSS PVSS UVSS AVSS TST VDD VSS All other pins are unconnected 19 4173CS-USB-07/04 Figure 2. IDL Test Condition, Idle Mode VDD RST VSS VDD PVDD UVDD AVDD IDL (NC) Clock Signal X2 X1 P0 VSS PVSS UVSS AVSS TST VDD VSS All other pins are unconnected Figure 3. IPD Test Condition, Power-Down Mode VDD RST VSS VDD PVDD UVDD AVDD P0 MCMD MDAT TST IPD VDD (NC) X2 X1 VSS PVSS UVSS AVSS VSS All other pins are unconnected 20 AT89C5132 4173CS-USB-07/04 AT89C5132 A-to-D Converter Table 2. A-to-D Converter DC Characteristics VDD = 2.7 to 3.3V , TA = -40C to +85C Symbol AVDD AIDD AIPD AVIN AVREF RREF CIA Parameter Analog Supply Voltage Analog Operating Supply Current Analog Standby Current Analog Input Voltage Reference Voltage AREFN AREFP AREF Input Resistance Analog Input capacitance AVSS AVSS 2.4 10 Min 2.7 Typ Max 3.3 600 Units V A A V AVDD = 3.3V AIN1:0 = 0 to AVDD AVDD = 3.3V ADEN = 0 or PD = 1 Test Conditions 2 AVDD AVDD 30 10 V V k pF TA = 25C TA = 25C Oscillator and Crystal Schematic Figure 4. Crystal Connection X1 C1 Q C2 VSS X2 Note: For operation with most standard crystals, no external components are needed on X1 and X2. It may be necessary to add external capacitors on X1 and X2 to ground in special cases (max 10 pF). X1 and X2 may not be used to drive other circuits. Parameters Table 3. Oscillator and Crystal Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85C Symbol CX1 CX2 CL DL F RS CS Parameter Internal Capacitance (X1 - VSS) Internal Capacitance (X2 - VSS) Equivalent Load Capacitance (X1 - X2) Drive Level Crystal Frequency Crystal Series Resistance Crystal Shunt Capacitance Min Typ 10 10 5 50 20 40 6 Max Unit pF pF pF W MHz pF 21 4173CS-USB-07/04 Phase Lock Loop Schematic Figure 5. PLL Filter Connection FILT R C1 VSS VSS C2 Parameters Table 4. PLL Filter Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85C Symbol R C1 C2 Parameter Filter Resistor Filter Capacitance 1 Filter Capacitance 2 Min Typ 100 10 2.2 Max Unit nF nF USB Connection Schematic Figure 6. USB Connection VBUS D+ DGND VSS To Power Supply RUSB D+ D- RUSB Parameters Table 1. USB Termination Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85C Symbol RUSB Parameter USB Termination Resistor Min Typ 27 Max Unit In-system Programming Schematic Figure 7. ISP Pull-down Connection ISP RISP VSS Parameters Table 5. ISP Pull-Down Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85C Symbol RISP Parameter ISP Pull-Down Resistor Min Typ 2.2 Max Unit k 22 AT89C5132 4173CS-USB-07/04 AT89C5132 AC Characteristics External 8-bit Bus Cycles Definition of Symbols Table 1. External 8-bit Bus Cycles Timing Symbol Definitions Signals A D L Q R W Address Data In ALE Data Out RD WR H L V X Z Conditions High Low Valid No Longer Valid Floating Timings Test conditions: capacitive load on all pins = 50 pF. Table 2. External 8-bit Bus Cycle - Data Read AC Timings VDD = 2.7 to 3.3V, TA = -40 to +85C Variable Clock Standard Mode Symbol TCLCL TLHLL TAVLL TLLAX TLLRL TRLRH TRHLH TAVDV TAVRL TRLDV TRLAZ TRHDX TRHDZ Parameter Clock Period ALE Pulse Width Address Valid to ALE Low Address hold after ALE Low ALE Low to RD Low RD Pulse Width RD high to ALE High Address Valid to Valid Data In Address Valid to RD Low RD Low to Valid Data RD Low to Address Float Data Hold After RD High Instruction Float After RD High 0 2*TCLCL-25 4*TCLCL-30 5*TCLCL-30 0 0 TCLCL-25 Min 50 2*TCLCL-15 TCLCL-20 TCLCL-20 3*TCLCL-30 6*TCLCL-25 TCLCL-20 TCLCL+20 9*TCLCL-65 2*TCLCL-30 2.5*TCLCL-30 0 Max Variable Clock X2 Mode Min 50 TCLCL-15 0.5*TCLCL-20 0.5*TCLCL-20 1.5*TCLCL-30 3*TCLCL-25 0.5*TCLCL-20 0.5*TCLCL+20 4.5*TCLCL-65 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 23 4173CS-USB-07/04 Table 3. External 8-bit Bus Cycle - Data Write AC Timings VDD = 2.7 to 3.3V, TA = -40 to +85C Variable Clock Standard Mode Symbol TCLCL TLHLL TAVLL TLLAX TLLWL TWLWH TWHLH TAVWL TQVWH TWHQX Parameter Clock Period ALE Pulse Width Address Valid to ALE Low Address hold after ALE Low ALE Low to WR Low WR Pulse Width WR High to ALE High Address Valid to WR Low Data Valid to WR High Data Hold after WR High Min 50 2*TCLCL-15 TCLCL-20 TCLCL-20 3*TCLCL-30 6*TCLCL-25 TCLCL-20 4*TCLCL-30 7*TCLCL-20 TCLCL-15 TCLCL+20 Max Variable Clock X2 Mode Min 50 TCLCL-15 0.5*TCLCL-20 0.5*TCLCL-20 1.5*TCLCL-30 3*TCLCL-25 0.5*TCLCL-20 2*TCLCL-30 3.5*TCLCL-20 0.5*TCLCL-15 0.5*TCLCL+20 Max Unit ns ns ns ns ns ns ns ns ns ns Waveforms Figure 1. External 8-bit Bus Cycle - Data Read Waveforms ALE TLHLL TLLRL TRLRH TRHLH RD TRLDV TRLAZ TAVLL P0 TLLAX A7:0 TAVRL TAVDV P2 A15:8 D7:0 Data In TRHDZ TRHDX 24 AT89C5132 4173CS-USB-07/04 AT89C5132 Figure 2. External 8-bit Bus Cycle - Data Write Waveforms ALE TLHLL TLLWL TWLWH TWHLH WR TAVWL TAVLL P0 TLLAX A7:0 TQVWH D7:0 Data Out P2 A15:8 TWHQX External IDE 16-bit Bus Cycles Definition of Symbols Table 4. External IDE 16-bit Bus Cycles Timing Symbol Definitions Signals A D L Q R W Address Data In ALE Data Out RD WR H L V X Z Conditions High Low Valid No Longer Valid Floating Timings Test conditions: capacitive load on all pins = 50 pF. 25 4173CS-USB-07/04 Table 5. External IDE 16-bit Bus Cycle - Data Read AC Timings VDD = 2.7 to 3.3V, TA = -40 to +85C Variable Clock Standard Mode Symbol Parameter TCLCL TLHLL TAVLL TLLAX TLLRL TRLRH TRHLH TAVDV TAVRL TRLDV TRLAZ TRHDX TRHDZ Clock Period ALE Pulse Width Address Valid to ALE Low Address hold after ALE Low ALE Low to RD Low RD Pulse Width RD high to ALE High Address Valid to Valid Data In Address Valid to RD Low RD Low to Valid Data RD Low to Address Float Data Hold After RD High Instruction Float After RD High 0 2*TCLCL-25 4*TCLCL-30 5*TCLCL-30 0 0 TCLCL-25 Min 50 2*TCLCL-15 TCLCL-20 TCLCL-20 3*TCLCL-30 6*TCLCL-25 TCLCL-20 TCLCL+20 9*TCLCL-65 2*TCLCL-30 2.5*TCLCL-30 0 Max Variable Clock X2 Mode Min 50 TCLCL-15 0.5*TCLCL-20 0.5*TCLCL-20 1.5*TCLCL-30 3*TCLCL-25 0.5*TCLCL-20 0.5*TCLCL+20 4.5*TCLCL-65 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Table 6. External IDE 16-bit Bus Cycle - Data Write AC Timings VDD = 2.7 to 3.3V, TA = -40 to +85C Variable Clock Standard Mode Symbol Parameter TCLCL TLHLL TAVLL TLLAX TLLWL TWLWH TWHLH TAVWL TQVWH TWHQX Clock Period ALE Pulse Width Address Valid to ALE Low Address hold after ALE Low ALE Low to WR Low WR Pulse Width WR High to ALE High Address Valid to WR Low Data Valid to WR High Data Hold after WR High Min 50 2*TCLCL-15 TCLCL-20 TCLCL-20 3*TCLCL-30 6*TCLCL-25 TCLCL-20 4*TCLCL-30 7*TCLCL-20 TCLCL-15 TCLCL+20 Max Variable Clock X2 Mode Min 50 TCLCL-15 0.5*TCLCL-20 0.5*TCLCL-20 1.5*TCLCL-30 3*TCLCL-25 0.5*TCLCL-20 2*TCLCL-30 3.5*TCLCL-20 0.5*TCLCL-15 0.5*TCLCL+20 Max Unit ns ns ns ns ns ns ns ns ns ns 26 AT89C5132 4173CS-USB-07/04 AT89C5132 Waveforms Figure 3. External IDE 16-bit Bus Cycle - Data Read Waveforms ALE TLHLL TLLRL TRLRH TRHLH RD TRLDV TRLAZ TAVLL P0 TLLAX A7:0 TAVRL TAVDV P2 A15:8 D15:81 Data In D7:0 Data In TRHDZ TRHDX Note: D15:8 is written in DAT16H SFR. Figure 4. External IDE 16-bit Bus Cycle - Data Write Waveforms ALE TLHLL TLLWL TWLWH TWHLH WR TAVWL TAVLL P0 TLLAX A7:0 TQVWH D7:0 Data Out P2 A15:8 D15:81 Data Out TWHQX Note: D15:8 is the content of DAT16H SFR. SPI Interface Definition of Symbols Table 7. SPI Interface Timing Symbol Definitions Signals C I O Clock Data In Data Out H L V X Z Conditions High Low Valid No Longer Valid Floating 27 4173CS-USB-07/04 Timings Table 8. SPI Interface Master AC Timing VDD = 2.7 to 3.3V, TA = -40 to +85C Symbol Parameter Slave Mode TCHCH TCHCX TCLCX TSLCH, TSLCL TIVCL, TIVCH TCLIX, TCHIX TCLOV, TCHOV TCLOX, TCHOX TCLSH, TCHSH TIVCL, TIVCH TCLIX, TCHIX TSLOV TSHOX TSHSL TILIH TIHIL TOLOH TOHOL Clock Period Clock High Time Clock Low Time SS Low to Clock edge Input Data Valid to Clock Edge Input Data Hold after Clock Edge Output Data Valid after Clock Edge Output Data Hold Time after Clock Edge SS High after Clock Edge Input Data Valid to Clock Edge Input Data Hold after Clock Edge SS Low to Output Data Valid Output Data Hold after SS High SS High to SS Low Input Rise Time Input Fall Time Output Rise Time Output Fall Time Master Mode TCHCH TCHCX TCLCX TIVCL, TIVCH TCLIX, TCHIX TCLOV, TCHOV TCLOX, TCHOX TILIH TIHIL TOLOH TOHOL Clock Period Clock High Time Clock Low Time Input Data Valid to Clock Edge Input Data Hold after Clock Edge Output Data Valid after Clock Edge Output Data Hold Time after Clock Edge Input Data Rise Time Input Data Fall Time Output Data Rise Time Output Data Fall Time 0 2 2 50 50 4 1.6 1.6 50 50 65 TOSC TOSC TOSC ns ns ns ns s s ns ns (1) Min Max Unit 8 3.2 3.2 200 100 100 100 0 0 100 100 130 130 TOSC TOSC TOSC ns ns ns ns ns ns ns ns ns ns 2 2 100 100 s s ns ns Notes: 1. Value of this parameter depends on software. 2. Test conditions: capacitive load on all pins = 100 pF 28 AT89C5132 4173CS-USB-07/04 AT89C5132 Waveforms Figure 5. SPI Slave Waveforms (SSCPHA = 0) SS (input) TSLCH TSLCL SCK (SSCPOL = 0) (input) SCK (SSCPOL = 1) (input) TSLOV MISO (output) SLAVE MSB OUT TIVCH TCHIX TIVCL TCLIX MOSI (input) MSB IN BIT 6 LSB IN TCLOV TCHOV BIT 6 TCHCH TCLCH TCLSH TCHSH TSHSL TCHCX TCLCX TCHCL TCLOX TCHOX SLAVE LSB OUT 1 TSHOX Note: 1. Not Defined but generally the MSB of the character which has just been received. Figure 6. SPI Slave Waveforms (SSCPHA = 1) SS1 (output) TCHCH SCK (SSCPOL = 0) (output) SCK (SSCPOL = 1) (output) TCLCH TCHCX TCLCX TCHCL TIVCH TCHIX TIVCL TCLIX MSB IN BIT 6 TCLOV TCHOV LSB IN TCLOX TCHOX LSB OUT Port Data SI (input) SO (output) Port Data MSB OUT BIT 6 Note: 1. Not Defined but generally the LSB of the character which has just been received. 29 4173CS-USB-07/04 Figure 7. SPI Master Waveforms (SSCPHA = 0) SS1 (input) TSLCH TSLCL SCK (SSCPOL = 0) (input) SCK (SSCPOL = 1) (input) TSLOV MISO (output) 1 SLAVE MSB OUT TIVCH TCHIX TIVCL TCLIX MOSI (input) MSB IN BIT 6 LSB IN TCHCH TCLCH TCLSH TCHSH TSHSL TCHCX TCLCX TCHCL TCHOV TCLOV BIT 6 TCHOX TCLOX SLAVE LSB OUT TSHOX Note: 1. SS handled by software using general purpose port pin. Figure 8. SPI Master Waveforms (SSCPHA = 1) SS1 (output) TCHCH SCK (SSCPOL = 0) (output) SCK (SSCPOL = 1) (output) TCLCH TCHCX TCLCX TCHCL TIVCH TCHIX TIVCL TCLIX SI (input) MSB IN TCLOV BIT 6 TCLOX TCHOX BIT 6 LSB IN SO (output) TCHOV Port Data MSB OUT LSB OUT Port Data Note: 1. SS handled by software using general purpose port pin. 30 AT89C5132 4173CS-USB-07/04 AT89C5132 Two-wire Interface Timings Table 1. TWI Interface AC Timing VDD = 2.7 to 3.3 V, TA = -40 to +85C INPUT Min Max 14*TCLCL(4) 16*TCLCL(4) 14*TCLCL(4) 1 s 0.3 s 250 ns 250 ns 250 ns 0 ns 14*TCLCL(4) 14*TCLCL(4) 14*TCLCL(4) 1 s 0.3 s OUTPUT Min Max 4.0 s(1) 4.7 s(1) 4.0 s(1) -(2) 0.3 s(3) 20*TCLCL(4)- TRD 1 s(1) 8*TCLCL(4) 8*TCLCL(4) - TFC 4.7 s(1) 4.0 s(1) 4.7 s(1) -(2) 0.3 s(3) Symbol THD; STA TLOW THIGH TRC TFC TSU; DAT1 TSU; DAT2 TSU; DAT3 THD; DAT TSU; STA TSU; STO TBUF TRD TFD Parameter Start condition hold time SCL low time SCL high time SCL rise time SCL fall time Data set-up time SDA set-up time (before repeated START condition) SDA set-up time (before STOP condition) Data hold time Repeated START set-up time STOP condition set-up time Bus free time SDA rise time SDA fall time Notes: 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 s. 3. Spikes on the SDA and SCL lines with a duration of less than 3*TCLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL= 400 pF. 4. TCLCL= TOSC= one oscillator clock period. Waveforms Figure 9. Two Wire Waveforms START or Repeated START condition Trd SDA (INPUT/OUTPUT) Tfd Trc SCL (INPUT/OUTPUT) Thd;STA Tlow Thigh Tsu;DAT1 Thd;DAT Tsu;DAT2 Tfc Tsu;STO Tsu;DAT3 0.7 VDD 0.3 VDD Tbuf Repeated START condition START condition STOP condition Tsu;STA 0.7 VDD 0.3 VDD 31 4173CS-USB-07/04 MMC Interface Definition of Symbols Table 9. MMC Interface Timing Symbol Definitions Signals C D O Clock Data In Data Out H L V X Conditions High Low Valid No Longer Valid Timings Table 10. MMC Interface AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85C, CL 100pF (10 cards) Symbol TCHCH TCHCX TCLCX TCLCH TCHCL TDVCH TCHDX TCHOX TOVCH Parameter Clock Period Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Input Data Valid to Clock High Input Data Hold after Clock High Output Data Hold after Clock High Output Data Valid to Clock High 3 3 5 5 Min 50 10 10 10 10 Max Unit ns ns ns ns ns ns ns ns ns Waveforms Figure 10. MMC Input Output Waveforms TCHCH TCHCX MCLK TCHCL TCHIX MCMD Input MDAT Input TCHOX MCMD Output MDAT Output TOVCH TCLCH TIVCH TCLCX 32 AT89C5132 4173CS-USB-07/04 AT89C5132 Audio Interface Definition of Symbols Table 11. Audio Interface Timing Symbol Definitions Signals C O S Clock Data Out Data Select H L V X Conditions High Low Valid No Longer Valid Timings Table 12. Audio Interface AC timings VDD = 2.7 to 3.3V, TA = -40 to +85C, CL 30pF Symbol TCHCH TCHCX TCLCX TCLCH TCHCL TCLSV TCLOV Parameter Clock Period Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Clock Low to Select Valid Clock Low to Data Valid 30 30 10 10 10 10 Min Max 325.5(1) Unit ns ns ns ns ns ns ns Note: 32-bit format with Fs = 48 kHz. Waveforms Figure 11. Audio Interface Waveforms TCHCH TCHCX DCLK TCHCL TCLSV DSEL TCLOV DDAT Right Left TCLCH TCLCX 33 4173CS-USB-07/04 Analog to Digital Converter Definition of Symbols Table 13. Analog to Digital Converter Timing Symbol Definitions Signals C E S Clock Enable (ADEN bit) Start Conversion (ADSST bit) H L Conditions High Low Characteristics Table 2. Analog to Digital Converter AC Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85C Symbol TCLCL TEHSH TSHSL DLe Parameter Clock Period Start-up Time Conversion Time Differential nonlinearity error(1)(2) Integral nonlinearity errorss(1)(3) Offset error(1)(4) Gain error(1)(5) Min 4 4 11*TCLCL 1 Max Unit s s s LSB ILe OSe Ge 2 4 4 LSB LSB LSB Notes: 1. AVDD= AVREFP= 3.0 V, AVSS= AVREFN= 0 V. ADC is monotonic with no missing code. 2. The differential non-linearity is the difference between the actual step width and the ideal step width (see Figure 23). 3. The integral non-linearity is the peak difference between the center of the actual step and the ideal transfer curve after appropriate adjustment of gain and offset errors (see Figure 23). 4. The offset error is the absolute difference between the straight line which fits the actual transfer curve (after removing of gain error), and the straight line which fits the ideal transfer curve (see Figure 23). 5. The gain error is the relative difference in percent between the straight line which fits the actual transfer curve (after removing of offset error), and the straight line which fits the ideal transfer curve (see Figure 23). Waveforms Figure 12. Analog-to-Digital Converter Internal Waveforms CLK TCLCL ADEN Bit TEHSH ADSST Bit TSHSL 34 AT89C5132 4173CS-USB-07/04 AT89C5132 Figure 13. Analog-to-Digital Converter Characteristics Code Out Offset Gain Error Error OSe Ge 1023 1022 1021 1020 1019 1018 Ideal Transfer Curve 7 6 5 4 3 2 1 0 0 1 LSB (Ideal) Center of a Step Example of an Actual Transfer Curve Integral Non-linearity (ILe) Differential Non-linearity (DLe) AVIN (LSBideal) 1 Offset Error OSe 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 Flash Memory Definition of Symbols Table 14. Flash Memory Timing Symbol Definitions Signals S R B ISP RST FBUSY flag L V X Conditions Low Valid No Longer Valid Timings Table 15. Flash Memory AC Timing VDD = 2.7 to 3.3V, TA = -40 to +85C Symbol TSVRL TRLSX TBHBL NFCY TFDR Parameter Input ISP Valid to RST Edge Input ISP Hold after RST Edge FLASH Internal Busy (Programming) Time Number of Flash Write Cycles Flash Data Retention Time 100K 10 Min 50 50 10 Typ Max Unit ns ns ms Cycle Year 35 4173CS-USB-07/04 Waveforms Figure 14. Flash Memory - ISP Waveforms RST TSVRL ISP(1) TRLSX Note: 1. ISP must be driven through a pull-down resistor (see Section "In-system Programming", page 22). Figure 15. Flash Memory - Internal Busy Waveforms FBUSY bit TBHBL External Clock Drive and Logic Level References Definition of Symbols Table 16. External Clock Timing Symbol Definitions Signals C Clock H L X Conditions High Low No Longer Valid Timings Table 17. External Clock AC Timings VDD = 2.7 to 3.3V, TA= -40 to +85C Symbol TCLCL TCHCX TCLCX TCLCH TCHCL TCR Parameter Clock Period High Time Low Time Rise Time Fall Time Cyclic Ratio in X2 Mode Min 50 10 10 3 3 40 60 Max Unit ns ns ns ns ns % Waveforms Figure 16. External Clock Waveform TCLCH TCHCX VDD - 0.5 0.45 V VIH1 TCLCX TCHCL TCLCL VIL 36 AT89C5132 4173CS-USB-07/04 AT89C5132 Figure 17. AC Testing Input/Output Waveforms INPUTS OUTPUTS VDD - 0.5 0.45 V 0.7 0.3 VDD VDD VIH min VIL max Notes: 1. During AC testing, all inputs are driven at VDD -0.5V for a logic 1 and 0.45V for a logic 0. 2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0. Figure 18. Float Waveforms VLOAD VLOAD + 0.1V VLOAD - 0.1V Timing Reference Points VOH - 0.1V VOL + 0.1V Note: For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs with IOL/IOH = 20 mA. 37 4173CS-USB-07/04 Ordering Information Possible Order Entries(1) Memory Size (Bytes) 64K Flash Part Number AT89C5132-ROTIL Supply Voltage 3V Temperature Range Industrial Max Frequency (MHz) 40 Package TQFP80 Packing Tray Product Marking 895132-IL Note: 1. PLCC84 package only available for development board. 38 AT89C5132 4173CS-USB-07/04 AT89C5132 Package Information TQFP80 39 4173CS-USB-07/04 PLCC84 40 AT89C5132 4173CS-USB-07/04 AT89C5132 Datasheet Change Log for AT89C5132 Changes from 4173A08/02 to 4173B-03/04 Changes from 4173B03/04 - 4173C - 07/04 1. Supression of ROM product version. 2. Supression of TQFP64 package. 1. Add USB connection schematic in USB section. 2. Add USB termination characteristics in DC Characteristics section. 3. Page access mode clarification in Data Memory section. 41 4173CS-USB-07/04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 literature@atmel.com Web Site http://www.atmel.com Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. (c) Atmel Corporation 2004. All rights reserved. Atmel(R) and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others. Printed on recycled paper. 4173CS-USB-07/04 /0M |
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